The present invention relates generally to a checksum adder, and more specifically, to a hardware circuit that is operable as a fixed point adder and a checksum adder.
A checksum or hash sum is a small-size datum computed from an arbitrary block of digital data for the purpose of detecting errors that may have been introduced during its transmission or storage. The actual procedure that yields the checksum given a data input is called a checksum function or checksum algorithm and will usually output a significantly different value even for small changes made to the input. Due to this property, they may be used to detect many data corruption errors and verify overall data integrity. That is, if the computed checksum for the current data input matches the stored value of a previously computed checksum, there is a very high probability the data has not been accidentally altered or corrupted.
Checksum addition was discussed in U.S. Pat. No. 8,554,822, filed on Jun. 24, 2010, the entire contents of which are incorporated herein by reference. According to that disclosure, checksum binary code decimal (BCD) arithmetic add/subtract operations are performed on two BCD numbers independent of which BCD number is of a greater magnitude. Such operations are responsive to the BCD arithmetic add/subtract operation being a subtract operation and include performing a BCD arithmetic subtraction operation on a first BCD number and a second BCD number, the first BCD number having a first magnitude and the second BCD number having a second magnitude.